Implement a testbench for the Verilog module

1. Every project in hardware needs a testbench to generate all necessary inputs and read outputs to ensure they are correct. This is very similar to writing test cases in software programming. The standard practice of naming a testbench is to add a "tb_" in front of the name of the module you are testing. A testbench is just another standard Verilog HDL File.

2. If you already have a file present in your directory, you can add/remove files to the project by navigating to “project->add/remove files in project”. Select the files -> apply -> ok.