Lab 2: Switch Inputs and Debouncing
Using switches as inputs to control LEDs.

Using switches as inputs to control LEDs.

Verilog HDL code

module Switch_LED_Control   (
    input wire [9:0] switches,   // 10 switches connected to FPGA
    output reg [9:0] leds        // 10 LEDs connected to FPGA
);

// Assign switch values to LED outputs
always @* begin
    // LEDR0 controlled by sw0
    leds[0] = switches[0];
    // LEDR1 controlled by sw1
    leds[1] = switches[1];
    // LEDR2 controlled by sw2
    leds[2] = switches[2];
    // Similarly, continue for other LEDs and switches
    // LEDR3 controlled by sw3
    leds[3] = switches[3];
    // LEDR4 controlled by sw4
    leds[4] = switches[4];
    // LEDR5 controlled by sw5
    leds[5] = switches[5];
    // LEDR6 controlled by sw6
    leds[6] = switches[6];
    // LEDR7 controlled by sw7
    leds[7] = switches[7];
    // LEDR8 controlled by sw8
    leds[8] = switches[8];
    // LEDR9 controlled by sw9
    leds[9] = switches[9];
end

endmodule

Pin Planner

Node NameDirectionLocationI/O BankVREF GroupFitter Location
switches[9]InputPIN_F157B7_N0PIN_F15
switches[8]InputPIN_B147B7_N0PIN_B14
switches[7]InputPIN_A147B7_N0PIN_A14
switches[6]InputPIN_A137B7_N0PIN_A13
switches[5]InputPIN_B127B7_N0PIN_B12
switches[4]InputPIN_A127B7_N0PIN_A12
switches[3]InputPIN_C127B7_N0PIN_C12
switches[2]InputPIN_D127B7_N0PIN_D12
switches[1]InputPIN_C117B7_N0PIN_C11
switches[0]InputPIN_C107B7_N0PIN_C10
leds[9]OutputPIN_B117B7_N0PIN_B11
leds[8]OutputPIN_A117B7_N0PIN_A11
leds[7]OutputPIN_D147B7_N0PIN_D14
leds[6]OutputPIN_E147B7_N0PIN_E14
leds[5]OutputPIN_C137B7_N0PIN_C13
leds[4]OutputPIN_D137B7_N0PIN_D13
leds[3]OutputPIN_B107B7_N0PIN_B10
leds[2]OutputPIN_A107B7_N0PIN_A10
leds[1]OutputPIN_A97B7_N0PIN_A9
leds[0]OutputPIN_A87B7_N0PIN_A8