Implementing debounce logic for switch inputs
In this lab, students will learn about the concept of debounce logic and its significance in digital systems. They will study Schmitt trigger inputs, which introduce hysteresis to the input signal, improving noise immunity and acting as a switch debouncer. Students will understand how Schmitt triggers help stabilize switch inputs by ensuring that a stable output is produced even in the presence of noisy or bouncing signals.
Lab Objective:
To learn and implement button debouncing techniques in Verilog and to utilize the SignalTap II Logic Analyzer to monitor and verify the functionality and stability of the debounced signals in real-time.
Required Tools and Components
- Intel Quartus Prime (with SignalTap II Logic Analyzer).
- DE10-Lite FPGA Development Board.
- USB cable for FPGA programming and debugging.
- Computers with Quartus Prime installed.
Pin Assignment of Push-buttons
| Signal Name | FPGA Pin No. | Description | I/O Standard |
|---|---|---|---|
| KEY0 | PIN_B8 | Push-button[0] | 3.3 V SCHMITT TRIGGER |
| KEY1 | PIN_A7 | Push-button[1] | 3.3 V SCHMITT TRIGGER |
Lab Setup and Implementation Guide
Verilog HDL code
module debounce(
input CLOCK_50,
input [1:0] KEY,
output [7:0] LED
);
reg [1:0] KEY_reg; // Previous state of KEY
reg [1:0] KEY_stable; // Stable state of KEY after debouncing
reg [19:0] debounce_count0 = 0; // Debounce counter for KEY[0]
reg [19:0] debounce_count1 = 0; // Debounce counter for KEY[1]
reg [7:0] count = 0; // Main counter for button presses
// Parameters for debounce threshold
parameter DEBOUNCE_LIMIT = 20'hFFFFF; // Adjust this threshold as needed for your environment
always @(posedge CLOCK_50) begin
// Debouncing for KEY[0]
if (KEY[0] == KEY_reg[0]) begin
debounce_count0 <= 0;
end else begin
if (debounce_count0 < DEBOUNCE_LIMIT)
debounce_count0 <= debounce_count0 + 1;
else begin
KEY_stable[0] <= KEY[0];
debounce_count0 <= 0;
end
end
// Debouncing for KEY[1]
if (KEY[1] == KEY_reg[1]) begin
debounce_count1 <= 0;
end else begin
if (debounce_count1 < DEBOUNCE_LIMIT)
debounce_count1 <= debounce_count1 + 1;
else begin
KEY_stable[1] <= KEY[1];
debounce_count1 <= 0;
end
end
KEY_reg <= KEY; // Update the previous state of KEY
// Increment main count on falling edge of debounced KEY[0]
if (KEY_stable[0] == 0 && KEY_reg[0] == 1)
count <= count + 1;
// Reset count on falling edge of debounced KEY[1]
if (KEY_stable[1] == 0 && KEY_reg[1] == 1)
count <= 0;
end
assign LED = count; // Display count on LEDs
endmodule
Pin Planner
| Node Name | Direction | Location | I/O Standard |
|---|---|---|---|
| CLOCK_50 | Input | PIN_P11 | 3 |
| KEY[1] | Input | PIN_A7 | 7 |
| KEY[0] | Input | PIN_B4 | 8 |
| LED[7] | Output | PIN_D14 | 7 |
| LED[6] | Output | PIN_E14 | 7 |
| LED[5] | Output | PIN_C13 | 7 |
| LED[4] | Output | PIN_D13 | 7 |
| LED[3] | Output | PIN_B10 | 7 |
| LED[2] | Output | PIN_A10 | 7 |
| LED[1] | Output | PIN_A9 | 7 |
| LED[0] | Output | PIN_A8 | 7 |
Explanation
This Verilog module named debounce is designed to handle button inputs from a two-button setup (KEY[0] and KEY[1]), apply debouncing to these inputs, and display the result on an 8-bit LED display. Debouncing is essential for reliable digital input from mechanical buttons or switches, which often generate noisy signals when pressed or released.
Setting Up Signal Tap Logic Analyzer
- Go to Tools > SignalTap II Logic Analyzer.
- Add a new SignalTap II file to your project.
- Insert KEY, KEY_reg, KEY_stable, debounce_count0, and debounce_count1 into the SignalTap setup.
- Set trigger conditions to capture the falling edge of KEY[0] and KEY[1].
Output
