module mux_2to1(
    input wire a, b,   // Boolean inputs
    input wire sel,    // Selector input
    output wire [6:0] out   // 7-segment output (A-G)
);

    wire mux_out;  // Intermediate wire for multiplexer output

    // 2-to-1 Multiplexer Logic
    assign mux_out = (sel) ? b : a;

    // Mapping multiplexer output to 7-segment display
    assign out = (sel & ~b) ? 7'b1000000 :   // 0 when sel=1 and b=0
                 (sel | a) ? 7'b1111001 :    // 1 when sel=0 and a=1, or sel=1 and b=1
                              7'b1111111;    // Otherwise, turn off all segments

endmodule

module mux_4to1(
    input wire [1:0] sel,     // Selector input
    input wire a1, a0,        // Input bits for a
    input wire b1, b0,        // Input bits for b
    output reg [6:0] out      // 7-segment output (A-G), changed to 'reg'
);

    // Enhanced mapping using truth table for multiplexer output to 7-segment display
    always @(*) begin
        case (sel)
            2'b00: out = 7'b1000000; // Output 0
            2'b01: out = 7'b1000000; // Output 0
            2'b10: begin
                case ({a1, a0})
                    2'b00: out = 7'b1000000; // Output 0
                    2'b01: out = 7'b1111001; // Output 1
                    2'b10: out = 7'b1000000; // Output 0
                    2'b11: out = 7'b1111001; // Output 1
                endcase
            end
            2'b11: begin
                case ({b1, b0})
                    2'b00: out = 7'b1000000; // Output 0
                    2'b01: out = 7'b1111001; // Output 1
                    2'b10: out = 7'b1000000; // Output 0
                    2'b11: out = 7'b1111001; // Output 1
                endcase
            end
        endcase
    end
endmodule