Displaying numbers on the seven-segment display
Verilog HDL Code
module hexTo7Seg(
input [3:0] hex_input,
output reg [6:0] seven_seg_out
);
always @*
case (hex_input)
4'b0000 : // Hexadecimal 0
seven_seg_out = 7'b1000000;
4'b0001 : // Hexadecimal 1
seven_seg_out = 7'b1111001;
4'b0010 : // Hexadecimal 2
seven_seg_out = 7'b0100100;
4'b0011 : // Hexadecimal 3
seven_seg_out = 7'b0110000;
4'b0100 : // Hexadecimal 4
seven_seg_out = 7'b0011001;
4'b0101 : // Hexadecimal 5
seven_seg_out = 7'b0010010;
4'b0110 : // Hexadecimal 6
seven_seg_out = 7'b0000010;
4'b0111 : // Hexadecimal 7
seven_seg_out = 7'b1111000;
4'b1000 : // Hexadecimal 8
seven_seg_out = 7'b0000000;
4'b1001 : // Hexadecimal 9
seven_seg_out = 7'b0011000;
4'b1010 : // Hexadecimal A
seven_seg_out = 7'b0001000;
4'b1011 : // Hexadecimal B
seven_seg_out = 7'b0000011;
4'b1100 : // Hexadecimal C
seven_seg_out = 7'b1000110;
4'b1101 : // Hexadecimal D
seven_seg_out = 7'b0100001;
4'b1110 : // Hexadecimal E
seven_seg_out = 7'b0000110;
4'b1111 : // Hexadecimal F
seven_seg_out = 7'b0001110;
default : // Other values
seven_seg_out = 7'b0000000; // Display nothing
endcase
endmodule
Pin Planner
| Node Name | Direction | Location | I/O Bank | VREF Group | Current Strength | Slew Rate |
|---|---|---|---|---|---|---|
| hex_input[0] | Input | PIN_C10 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| hex_input[1] | Input | PIN_C11 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| hex_input[2] | Input | PIN_D12 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| hex_input[3] | Input | PIN_C12 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[0] | Output | PIN_C14 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[1] | Output | PIN_E15 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[2] | Output | PIN_C15 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[3] | Output | PIN_C16 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[4] | Output | PIN_E16 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[5] | Output | PIN_D17 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |
| seven_seg_out[6] | Output | PIN_C17 | 7 | B7_N0 | 3.3-V LVTTL | 8mA (default) |